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s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 1 SED1540 cmos dot matrix lcd controller/driver s-mos systems, inc. october, 1996 version 1.0 (preliminary)
? s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 2 this page intentionally blank
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 3 table of contents 1.0 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.0 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 description of circuit blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.1 mpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.2 busy flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.3 display start line register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.4 column address counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.5 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.6 display data ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.7 common timing generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.8 display data latch circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.9 lcd driver circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.10 display timing generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.11 oscillation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.12 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.0 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 power signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 system bus interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 display on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 display start line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 set page address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 column address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 read status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 write display data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.7 read display data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.8 select adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.9 static drive on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.10 select duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
table of contents s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 4 4.11 read modify write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.11.1 cursor blinking sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.12 end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.12.1 end timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.13 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.14 save power (combined command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.14.1 external resistor division circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.1 system bus read/write i (80 family mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.2 system bus read/write ii (68 family mpu) . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.3 display control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.0 mpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1 80 family mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2 68 family mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.0 lcd driver interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1 SED1540 - SED1540 (internal oscillation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2 SED1540 - SED1540 (external clock operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.0 typical connections with lcd panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.1 typical connections with lcd panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.0 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 plastic qfp 5-100 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.0 pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.1 al pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.1.2 au bump pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.2 pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 5 1.0 general description 1.0 ?1.2 1.0 general description 1.1 description the SED1540 is an lcd driver-controller intended mainly for segment type liquid crystal displays. the device communicates with a host microprocessor through an 8-bit parallel data. the SED1540 stores the data that is sent from the microcomputer in the built-in data display ram, and generates a liquid drive signal. the device is manufactured with a low power consumption cmos process. these features give the designer a flexible means of implementing a small to medium size lcd display for a compact, low power system. 1.2 features low-power cmos technology fast cpu 8-bit data interface (80xx, 68xx) 1/4 duty cycle built-in lcd driver circuit . . . . . . . . . 73 segments 4 commons built-in display data ram. . . . . . . . . 2560 bits rich display command setting on-chip cr oscillation circuit master/slave operation is supported recommended expansion driver . . . sed1521(80-segment driver) low power consumption . . . . . . . . . 30 m w max lcd voltage . . . . . . . . . . . . . . . . . . . 3.5 to 11v single power supply. . . . . . . . . . . . . 2.4 to 7.0v package . . . . . . . . . . . . . . . . . . . . . . qfp5-100 pin (f oa ) al pad (d oa ) au bump (d ob ) clock source fcl frame frequency external clock 4 khz 85/64 hz internal oscillation 18 khz 375/281 hz
1.2 ?1.2 1.0 general description s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 6 this page intentionally blank
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 7 2.0 block diagrams 2.0 ?2.1 2.0 block diagrams 2.1 system block diagram 73 seg 4 com SED1540 cpu 80xx 68xx res cs d0 ~ d7 seg0~seg72 com0~com3
2.2 ?2.2 2.0 block diagrams s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 8 2.2 block diagram line address decoder display data ram 2560 bits i/o buffer internal bus low address register bus holder line counter display timing generator display start line register fr command decoder column address register status mpu interface column address counter column address decoder display data latch circuit lcd driver circuit common counter osc1 osc2 d 0 d a e , r/w res (rd)(wr) 0 , cs 7 ~ v dd v ss m/s v , v , v 123 ~ sg sg 072 ~ cm cm 03
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 9 2.0 block diagrams 2.3 ?2.3.1.3 2.3 description of circuit blocks 2.3.1 mpu interface 2.3.1.1 selection of interface type the SED1540 series uses 8 bits of bi-directional data bus (d 0 ? 7 ) to transfer data. the reset pin is capable of selecting mpu interface; setting the polarity of res to either ??or ??can provide direct interface of the SED1540 with a 68 or 80 family mpu (see table 1 below). with cs at high level, the SED1540 is independent from the mpu bus and stays in standby mode. in this mode, however, the reset signal is input independently of the internal status. table 1 2.3.1.2 identification of data bus signals the SED1540 uses a combination of a0, e, r/w, (rd , wr ) to identify a data bus signal. table 2 2.3.1.3 access to display data ram and internal register in order to make matching of operating frequencies between the mpu and the display data ram or internal register, the SED1540 performs a sort of lsi?si pipelining via the bus holder attached to the internal data bus. consider the case where the mpu reads the content of the display data ram. in the first data read cycle (dummy), the data is stored on the bus holder. in the next data read cycle, the data is read from the bus holder to the system bus. also, consider the case where the mpu writes data to the display data ram. in the first data write cycle, the data is held on the bus holder. the data is written to the display data ram before the next data write cycle begins. polarity of res type a 0 e r/w cs d0?7 ? active 68 mpu ---- - ? active 80 mpu - rd wr -- common 68 mpu 80 mpu function a0 r/w rd wr 1101 read display data 1010wr ite display data 0101 read status 0010wr ite to internal register (command)
2.3.1.4 ?2.3.1.5 2.0 block diagrams s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 10 therefore, mpu? access to the SED1540 is affected not by display data ram access time (t acc , t ds ) but by cycle time (t cyc ). this leads to faster transfer of data to and from the mpu. if the cycle time requirement is not met, the mpu has only to execute the nop instruction and this is appar- ently equivalent to execution of a waiting operation. however, there is a restriction on the read sequence of the display data ram; when an address is set, its data is output not to the first read instruction (immediately following the address setting operation) but to the second read instruction. thus, one dummy read cycle is necessary after an address set or write cycle. this relation is shown in figures 2.3.1.4 and 2.3.1.5. 2.3.1.4 write timing diagram 2.3.1.5 read timing diagram wr data mpu bus holder wr n n + 1 n + 2 n + 3 n + 2 n + 1 n n + 3 internal timing wr data mpu bus holder column address wr rd rd n address set at n dummy read data read at n data read at n+1 n n n+1 n + 1 n n n + 2 n + 2 n + 1 n internal timing
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 11 2.0 block diagrams 2.3.2 ?2.3.6 2.3.2 busy flag busy flag being ??means that the SED1540 is performing its internal operation and any instruction other than read status is disabled. the busy flag is output to pin d7 by a read status instruction. as long as the cycle time (t cyc ) requirement is met, the flag need not be checked before each com- mand and this dramatically improves the mpu performance. 2.3.3 display start line register this register is a pointer which determines the start line corresponding to com0 (normally, the up- permost line of display) for display of data in the display data ram. it is used for scrolling the dis- play or changing the page from one to another. executing the set display start line command sets 5 bits of display start address in this register. its content is preset in the line counter at each timing the fr signal changes. the line counter is incremented synchronously to a cl input, thus generating a line address for sequential reading of 80 bits of data from the display data ram to the lcd driver circuit. 2.3.4 column address counter the column address counter is a 7?it presettable counter which gives column addresses of the display data ram as shown in fig. 2.3.6.1. when a read/write display data command comes in, the counter is incremented by 1. for any nonexisting address over 50h, the counter is locked and not incremented. the column address counter is independent from the page register. 2.3.5 page register this register gives a page address of the display data ram as shown in fig. 2.3.6.1. the set page address command permits the mpu to access a new page of the display data ram. 2.3.6 display data ram dot data for display is stored in this ram. since the mpu and lcd driver circuit operate indepen- dently of each other, data can be changed asynchronously without adverse effect on the display. one bit of the display data ram is assigned to one bit of lcd: lcd on = ? lcd off = ? the adc command inverts the assignment relationship between a display data ram column ad- dress and a segment output (see fig. 2.3.6.1).
2.3.6.1 ?2.3.6.1 2.0 block diagrams s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 12 2.3.6.1 relationship between display data ram locations and addresses (duty = 1/4 and display starting line = 08) page address d 1 ,d 2 =0,0 0,1 1,0 1,1 com 0 1 2 3 data d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 page 0 page 1 page 2 page 3 start stop line address display disabled area associated line (ex.) assignment common output 00 h 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f column address adc display area seg pin seg 0 1 2 3 4 5 6 7 d 0 =? 4f h 4e 4d 4c 4b 4a 49 48 d 0 =? 00 h 01 02 03 04 05 06 07 77 78 79 02 01 00 4d 4e 4f 73 06 49
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 13 2.0 block diagrams 2.3.7 ?2.3.11 2.3.7 common timing generator this circuit generates common timing and frame (fr) signals from the basic clock (cl). the se- lect duty command selects a duty of 1/3 or 1/4. 2.3.8 display data latch circuit the display data latch circuit temporarily stores the data which will be output from the display data ram to the lcd driver circuit at one-common intervals. the display on/off and static driver on/off commands control the latched data so that the data in the display data ram remains unchanged. 2.3.9 lcd driver circuit this circuit generates 77 sets of multiplexer that generate quartet levels for lcd driving. display data in the display data latch, common timing generator output and fr signal are combined to out- put an lcd driving waveform (fig. 2.3.12.1). 2.3.10 display timing generator this circuit generates an internal display timing signal from the basic clock (osc1) and frame signal (fr). the frame signal fr makes the lcd driver circuit generate a dual frame ac driving waveform (type b) to drive lcd, while making both the line counter and common timing generator synchro- nized to the fr signal output lsi (dedicated common driver or the SED1540 master lsi). to achieve these functions, the fr signal must be a clock with a duty of 50% which is synchronized to the frame period. clock osc1 is used to operate the line counter. if it is given from outside the lsi, a clock with a duty of 50% is input to osc1 for the master drive and a clock whose phase is inverted to the clock for the master is input to osc2 for the slave driver. (instead, osc2 for the master driver may be input to osc2 for the slave driver.) 2.3.11 oscillation circuit this circuit is a low-power cr oscillator which uses an oscillation resistor rf alone to adjust the oscillation frequency. it generates display timing signals. fig. 4???? shows the relation between the oscillation resistor and the oscillation frequency that corresponds to the SED1540? frame fre- quency. when rf is 1.0m w , frame frequency is about 280hz.
2.3.11.1 ?2.3.11.2 2.0 block diagrams s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 14 2.3.11.1 lsi containing oscillator * as the parasitic capacitance in this portion increases, the oscillation frequency will shift to a lower level. the rf must have a smaller value than the specification. * for a system having two or more slave lsis, a cmos buffer is necessary. 2.3.11.2 lsi operating with external clock master lsi osc1 m/s v dd v ss osc2 r f *1 *2 ( ) slave lsi osc1 open m/s osc2 clock source (mpu) cl SED1540 slave osc2 osc1 m/s osc2
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 15 2.0 block diagrams 2.3.12 ?2.3.12 2.3.12 reset circuit this circuit senses the leading edge or trailing edge of res and initializes the system when its power is switched on. initialization: (a) display off (b) display start line register: first line (c) static drive off (d) column address counter: address 0 (e) page address register: page 0 (f) select duty: 1/4 (g) select adc: forward (adc command d0 = ?? adc status flag = ?? (h) read modify write off the input at pin res is level-sensed to select an mpu interface mode as shown in table 1. for interfacing with an 80 family mpu, an ??active reset signal is input to pin res . for interfacing with a 68 family mpu, an ??active reset signal is input to the pin. (see fig.6.)????? as exemplified in section 6 ?pu interface? pin res is connected to the mpu reset pin. thus the SED1540 and the mpu are initialized at the same time. if system is initialized by pin res at power- on, it may no longer be reset. the reset command causes initialization (b), (d) and (e).
2.3.12.1 ?2.3.12.1 2.0 block diagrams s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 16 2.3.12.1 examples of lcd driving waveform fr v dd v dd v 1 v 2 v 3 v dd v 1 v 2 v 3 v dd v 1 v 2 v 3 v dd v 1 v 2 v 3 v dd v 1 v 2 v 3 v 3 v 2 v 1 ? 1 ? 2 ? 3 0v v 1 ? 1 0v v ss com0 com1 com2 com3 segn com3~segn com0~segn
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 17 3.0 pin configuration 3.0 ?3.1 3.0 pin configuration 3.1 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 seg71 seg70 seg69 seg68 seg67 seg66 seg65 seg64 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 db1 db0 v ss r/w(wr) e(rd) osc2 osc1 a0 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 seg72 com3 com2 com1 com0 v1 v2 m/s nc cs v3 fr res v dd db7 db6 db5 db4 db3 db2 SED1540f oa
3.1 ?3.1 3.0 pin configuration s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 18 number name number name number name number name 1 seg71 26 seg46 51 seg21 76 e(rd ) 2 seg70 27 seg45 52 seg20 77 r/w (wr ) 3 seg69 28 seg44 53 seg19 78 v ss 4 seg68 29 seg43 54 seg18 79 db0 5 seg67 30 seg42 55 seg17 80 db1 6 seg66 31 seg41 56 seg16 81 db2 7 seg65 32 seg40 57 seg15 82 db3 8 seg64 33 seg39 58 seg14 83 db4 9 seg63 34 seg38 59 seg13 84 db5 10 seg62 35 seg37 60 seg12 85 db6 11 seg61 36 seg36 61 seg11 86 db7 12 seg60 37 seg35 62 seg10 87 v dd 13 seg59 38 seg34 63 seg9 88 res 14 seg58 39 seg33 64 seg8 89 fr 15 seg57 40 seg32 65 seg7 90 v 3 16 seg56 41 seg31 66 seg6 91 cs 17 seg55 42 seg30 67 seg5 92 nc 18 seg54 43 seg29 68 seg4 93 m/s 19 seg53 44 seg28 69 seg3 94 v 2 20 seg52 45 seg27 70 seg2 95 v 1 21 seg51 46 seg26 71 seg1 96 com0 22 seg50 47 seg25 72 seg0 97 com1 23 seg49 48 seg24 73 a 0 98 com2 24 seg48 49 seg23 74 osc1 99 com3 25 seg47 50 seg22 75 osc2 100 seg72 duty pin 98 99 1/4 com2 com3 1/3 nc com2
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 19 3.0 pin configuration 3.2 ?3.2.2 3.2 pin description 3.2.1 power signals v dd connected to +5v power. common to mpu power pin v cc . v ss 0v, connected to system gnd. v 1 ? 3 multi-level power used to drive lcds. voltage specified to each lcd cell is divided by resistors or impedance-converted by an operational amplifier before being applied. each voltage to be applied must be based on v dd , while fulfilling the following conditions: v dd 3 v 1 3 v 2 3 v 3 3.2.2 system bus interface signals d 7 ? 0 8?it, tri-state, bi-directional i/o bus. normally, connected to the data bus of an 8?16 bit standard microcomputer. a 0 input pin. normally, the lsb of the mpu address bus is connected to this input pin to provide data/command selection. 0: display control data on d 0 ? 7 1: display data on d 0 ? 7 res input pin. the SED1540 can be reset or initialized by setting res to low level (if it is interfaced with a 68 family mpu) or high level (if with an 80 family mpu). this reset op- eration occurs when an edge of the res signal is sensed. the level input selects the type of interface with the 68 or 80 family mpu: high level: interface with 68 family mpu low level: interface with 80 family mpu cs chip select input signal which is normally obtained by decoding an address bus signal. effective with ??active and a chip operating with external clocks. e(rd ) chip interfaced with 68 family mpu: enable clock signal input for the 68 family mpu. chip interfaced with 80 family mpu: ??active input pin to which the 80 family mpu rd signal is connected. with this signal held at ?? the SED1540 data bus works as output.
3.2.2.1 ?3.2.2.1 3.0 pin configuration s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 20 r/w (wr ) chip interface with 68 family mpu: read/write control signal input pin. r/w = ??: read r/w = ??: write chip interfaced with 80 family mpu: ??active input pin to which the 80 family wr is connected. the signal on the data bus is fetched by the leading edge of wr . osc1 connects a resistor for internal oscillation. when m/s = ?? internal oscillation is osc2 disabled and the osc2 works as an input pin for a clock whose phase is opposite to the clock to the osc1. with the power-save function active, oscillation or clock input is disabled and the osc2 turns to high impedance. (see the description of each block.) fr lcd ac signal i/o pin. i/o selection: m/s = 1: output m/s = 0: input seg0 lcd segment driving output pins. one of the v dd , v 1 , v 2 , and v 3 levels is selected seg72 by a combination of the content of the display ram and the fr signal. 3.2.2.1 lcd segment driving output timing fr data 1 1 v dd v 2 v 3 v 1 0 0 10 output level
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 21 3.0 pin configuration 3.2.2.2 ?3.2.2.2 com0 lcd common (row) driving output. (the com2 and com3 output state is changed by com3 the duty select command. one of the v dd , v 1 , v 2 , and v 3 levels is selected by a com- bination of the output of the common counter output and the fr signal. 3.2.2.2 lcd common (row) driving output m/s input signal which selects the master or slave operation for the SED1540. connected to v dd or v ss . the ms pin changes the i/o state of the fr, osc1, and osc2 pins. m/s = v dd : master m/s = v ss : slave * using fr to synchronize the master ic with the slave ic provides a com output of the same waveform for both ics. m/s fr osc1 osc2 com output v dd output input output valid v ss input nc input valid* fr counter output 1 1 v 3 v 1 v dd v 2 0 0 10 output level
3.2.2.2 ?3.2.2.2 3.0 pin configuration s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 22 this page intentionally blank
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 23 4.0 commands 4.0 ?4.2 4.0 commands table 3 lists the commands used with the SED1540. this lsi uses a combination of a 0 , r/w (rd , wr ) to identify a data bus signal. interpretation and execution of a command depends not on ex- ternal clock but on internal timing alone. therefore, a command can be executed so fast that no busy check is needed. a detailed description of commands follows. 4.1 display on/off this command forces all display to turn on or off. d 0 = display off 1 = display on 4.2 display start line this command specifies a line address (shown in fig. 2.3.6.1) thus marking the display line that corresponds to com0. display begins with the specified line address and covers as many lines as match the display duty in address ascending order. dynamic line address change with the display start line command enables column-wise scrolling or page change. ?high-order bits r/w a0 rd wr d7 d0 0101010111d r/w a0 rd wr d7 d0 010110a 4 a 3 a 2 a 1 a 0 a4 a3 a2 a1 a0 line address 00000 0 00001 1 11111 31
4.3 ?4.4 4.0 commands s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 24 4.3 set page address this command is used to specify a page address equivalent to a row address for mpu access to the display data ram. a required bit of the display data ram can be accessed by specifying its page address and column address. changing the page address causes no change in display. 4.4 column address this command specifies a display data ram column address. the column address is incremented by 1 each time the mpu accesses from the set address to the display data ram. thus, it is pos- sible for the mpu to gain continuous access to only the data. this incrementing stops with address 80; the page address is not continuously changed. r/w a0 rd wr d7 d0 010101110a 1 a 0 a1 a0 page 00 0 01 1 10 2 11 3 r/w a0 rd wr d7 d0 0100a 6 a 5 a 4 a 3 a 2 a 1 a 0 a6 a5 a4 a3 a2 a1 a0 column address 0000000 0 0000001 1 1001111 79
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 25 4.0 commands 4.5 ?4.6 4.5 read status busy: busy being ??means that system is performing an internal operation or is reset. no command is accepted before busy = ?? as long as the cycle time requirement is met, no busy check is needed. adc: indicates assignment of column addresses to segment drivers. 0: inverted (column address 79? ? segment driver n) 1: forward (column address n ? segment driver n) on/off: indicates display on or off. 0: display on 1: display off this bit has polarity reverse to the display on/off command. reset: indicates that system is being initialized by the res signal or the reset command. 0: display mode 1: being reset 4.6 write display data this command allows the mpu to write 8 bits of data into the display data ram. once the data is written, the column address is automatically incremented by 1; this enables the mpu to write multi- word data continuously. r/w a0 rd wr d7 d0 001 busy adc on/ off reset 0000 r/w a0 rd wr d7 d0 1 1 0 write data
4.7 ?4.9 4.0 commands s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 26 4.7 read display data this command allows the mpu to read 8 bits of data from the display data ram location specified by a column address and a page address. once the data is read, the column address is automat- ically incremented by 1; this enables the mpu to read multi-word data continuously. a dummy read is needed immediately after the column address is set. for details, see 3. (1)?c)?? 4.8 select adc this command inverts the relation of assignment between display data ram column addresses and segment driver outputs. in other words, the select adc command can software-invert the or- der of segment driver output pins, reducing the restrictions on the configuration of ics at lcd mod- ule assembly. for details, see fig. 2.3.6.1. incrementing the column address by 1, which takes place after the mpu writing or reading display data, follows the sequence of column addresses specified in fig. 2.3.6.1. d = 0: clockwise output (forward) d = 1: counterclockwise output (reverse) 4.9 static drive on/off this command forces all display to be on and, at the same time, all common output to be selected. d = 0: static drive off d = 1: static drive on r/w a0 rd wr d7 d0 1 0 1 read data r/w a0 rd wr d7 d0 0101010000d r/w a0 rd wr d7 d0 0101010010d
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 27 4.0 commands 4.10 ?4.11 4.10 select duty this command is used to select the duty (degree of multiplexity) of lcd driving. d = 0: duty 1/3 d = 1: duty 1/4 4.11 read modify write this command is used with the end command in a pair. once it has been entered, the column address will be incremented not by the read display data command but by the write display data command only. this mode will stay until the end command is entered. entry of the end command causes the column address to return to the address which was valid when the read modify write command was entered. this function lessens the load of the mpu when the data in a specific display area are repeatedly updated (as blinking cursor). even in the read modify write mode, any command other than read/write data and set column address may be used. r/w a0 rd wr d7 d0 0101010100d r/w a0 rd wr d7 d0 01011100000
4.11.1 ?4.11.1 4.0 commands s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 28 4.11.1 cursor blinking sequence page address set column address set read modify write dummy read data read data write no end modify ended?
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 29 4.0 commands 4.12 ?4.13 4.12 end this command cancels the read modify write command, returning the column address to the ini- tial mode address. 4.12.1 end timing 4.13 reset this command initializes the display start line register, column address counter, and page address counter without any effect on the display data ram. for details, see section 2.3.12. the reset operation follows entry of the reset command. initialization at power-on is performed not by the reset command but by a reset signal applied to the res pin. r/w a0 rd wr d7 d0 01011101110 r/w a0 rd wr d7 d0 01011100010 n + 1 n n + 2 n n + m column address read modify write mode set end return
4.14 ?4.14.1 4.0 commands s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 30 4.14 save power (combined command) static drive going on with display off invokes power-saving mode, reducing current consumption to nearly static current level. during this mode, the SED1540 holds the following conditions: (a) it stops driving the lcd; the segment and common driver outputs are at v dd level. (b) oscillation and external clock input are disabled; osc2 is in floating condition. (c) the display data and operational mode are held. the power-saving mode is cancelled by display on or static drive off. if an external resistor division circuit is used to give lcd driving voltage level, the current flowing into the resistors must be cut off by the power-save signal. 4.14.1 external resistor division circuit v dd power save signal v ssh v dd v 1 v 2 v 3 r r r SED1540
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 31 4.0 commands 4.14.1 ?4.14.1 table 3 commands * with display off (command (1)), static drive going on (9) invokes power-saving mode. command code function a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (1) display on/off 0 1 0 10101110/1 turns all display on or off, independently of dis- play ram data or internal status. 1: on 0: off (power-saving mode with static drive on)* (2) display start line 0 1 0 1 1 0 display start address (0?1) speci?s ram line corresponding to uppermost line (com0) of display. (3) set page address 0 1 0 101110 page (0?) sets display ram page in page address register. (4) set column (segment) address 0 1 0 0 column address (0?2) sets display ram column address in column address register. (5) read status 0 0 1 busy adc on/off reset 0000 reads the following status: busy 1: internal operation, 0: ready adc 1: cw output (forward), 0: ccw output (reverse) on/off 1: display off, 0: display on reset 1: being reset, 0: normal (6) write display data 1 1 0 write data writes data from data bus into display ram. display ram location whose address has been preset is accessed. after access, the column address is incremented by 1. (7) read display data 1 0 1 read data reads data from display ram onto data bus. (8) select adc 0 1 0 10100000/1 used to invert relationship of assignment between display ram column addresses and segment driver outputs. 0: cw output (forward) 1: ccw output (reverse) (9) static drive on/ off 0 1 0 10100100/1 selects normal display or static driving operation. 1: static drive (power-saving mode) 0: normal driving (10) select duty 0 1 0 10101000/1 selects lcd cell driving duty. 1: 1/4 0: 1/3 (11) read modify write 0 1 0 11100000 increments column address counter by 1 when display data is written. (this is not done when data is read.) (12) end 0 1 0 11101110 clears read modify write mode. (13) reset 0 1 0 11100010 sets display start line register on the ?st line. also sets column address counter and page address counter to 0.
4.14.1 ?4.14.1 4.0 commands s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 32 this page intentionally blank
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 33 5.0 electrical characteristics 5.0 ?5.1 5.0 electrical characteristics 5.1 absolute maximum ratings notes: 1. all voltages are based on v dd = 0v. 2. the following condition must always hold true with voltages v 1 , v 2 and v 3 : v dd 3 v 1 3 v 2 3 v 3 . 3. the lsi may be permanently damaged if used with any value in excess of the absolute maximum ratings. during normal operation, the lsi should preferably be used within the specified electrical characteristics. failure to meet them can cause the lsi to malfunction or lose its reliability. 4. generally, flat package lsis may have moisture resistance lowered when solder dipped. in mounting lsis on a board, it is recommended to use a method which is least unlikely to give thermal stress on the package resin. parameter symbol standard unit supply voltage (1) v ss ?.0 ~ +0.3 v supply voltage (2) v 3 ?5.0 ~ + 0.3 v supply voltage (3) v 1 , v 2 ,v 3 v 3 ~ + 0.3 v input voltage v in v ss ?0.3 ~ + 0.3 v output voltage v o v ss ?0.3 ~ + 0.3 v power dissipation p d 250 mw operating temperature t opr ?0 ~ +85 c storage temperature fp t stg ?5 ~ +150 c bare chip ?5 ~ +125 soldering temperature/time t solder 260/10 (at leads) c/sec
5.2 ?5.2 5.0 electrical characteristics s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 34 5.2 dc characteristics v dd = 0v, ta = ?0 ~ 75 c parameter symbol condition min. typ. max. unit applicable pin operating voltage (1)* 1 recommended v ss ?.5 ?.0 ?.5 vv ss allowable ?.0 ?.4 operating voltage (2) recommended v 3 ?1.0 ?.5 vv 3 *10 allowable ?1.0 allowable v 1 0.6 v 3 v dd vv 1 allowable v 2 v 3 0.4 v 3 vv 2 high level input voltage v iht v ss + 2.0 v dd v *2 *3 v ihc 0.2 v ss v dd low level input voltage v ilt v ss v ss + 0.8 v *2 *3 v ilc v ss 0.8 v ss high level output voltage v oht i oh = ?.0ma v ss + 2.4 v *4 v ohc1 i oh = ?.0ma v ss + 2.4 *5 v ohc2 i oh = ?20 m a 0.2 v ss osc2 low level output voltage v olt i ol = 3.0ma v ss + 0.4 v *4 v olc1 i ol = 2.0ma v ss + 0.4 *5 v olc2 i ol = 120 m a 0.8 v ss osc2 input leakage current i li ?.0 1.0 m a*6 output leakage current i lo ?.0 3.0 m a*7 lcd driver on resistor r on ta = 25 c v 3 = ?.0v 5.0 7.5 k w seg 0 ~ 72 *11 com 0 ~ 3 v 3 = ?.5v 10.0 50.0 static current dissipation i ddq cs = cl = v dd 0.05 1.0 m av dd dynamic current dissipation i dd (1) during display v 3 = ?.0v f osc = 4khz 1.5 4.0 m a v dd r f = 1m w 9.5 15.0 i dd (2) during access t cyc = 200khz 300 500 *8 input pin capacitance c in ta = 25 c f = 1mhz 5.0 8.0 pf all input pins
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 35 5.0 electrical characteristics 5.2 ?5.2 notes: *1. operation over a wide range of voltages is guaranteed except where a sudden voltage change occurs during access. *2. pins a 0 , d 0 ? 7 , e(rd ), r/w (wr ) and cs *3. pins cl, fr, m/s and res *4. pins d 0 ? 7 *5. pin fr *6. pins a 0 , e (rd ), r/w (wr ), cs , cl and res *7. applicable when pins d 0 ? 7 and fr are at high impedance. *8. this value is current consumption when a vertical stripe pattern is written at t cyc . *9. relationship between oscillation frequency, frame and rf (SED1540) oscillation frequency f osc rf = 1.0m w 2% v ss = ?.0v 15 18 21 khz *9 rf = 1.0m w 2% v ss = ?.0v 11 16 21 reset time t r 1.0 1000 m s res (continued) v dd = 0v, ta = ?0 ~ 75 c parameter symbol condition min. typ. max. unit applicable pin 40 30 20 10 0 f osc (khz) rf (m ) 0.5 1.5 2.5 2.0 1.0 ta = 25 c v ss = ?v 800 400 0 frame (hz) rf (m ) 0.5 1.5 2.5 2.0 1.0 ta = 25 c v ss = ?v duty 1/4 duty 1/3 rf osc1 osc2
5.2 ?5.2 5.0 electrical characteristics s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 36 notes (continued): relationship between external clock (fcl) and frame (SED1540) *10.operating voltage ranges of v ss and v 3 *11.resistance with a voltage of 0.1v applied between the output pin (seg, com) and each power pin (v 1 , v 2 ). it is specified within the operating voltage (2) range. 200 100 0 duty 1/4 duty 1/3 frame (hz) f osc (khz) 12 8 4 operating voltage range ?5 ?0 ? 0 v 3 (v) v ss (v) ? ? ? ?
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 37 5.0 electrical characteristics 5.3 ?5.3.1 5.3 timing characteristics 5.3.1 system bus read/write i (80 family mpu) *1. each of the values where v ss = ?.0v is about 200% of that where v ss = ?.0v (i.e., the listed value). *2. the rise or fall time of input signals should be less than 15 ns. ta = ?0 to 75 c, v ss = ?.0v 10%, unit: ns signal symbol parameter min. max. condition a 0 , cs t ah8 t aw8 address hold time address setup time 10 20 wr , rd t cyc8 t cc system cycle time control pulse width 1000 200 d 0 ? 7 t ds8 data setup time 80 t dh8 data hold time 10 t acc8 rd access time 90 cl = 100pf t oh8 output disable time 10 60 a0, cs wr, rd d0 ~ d7 d0 ~ d7 (write) t ah8 (read) t cyc8 t aw8 t ds8 t dh8 t oh8 t acc8 t cc
5.3.2 ?5.3.2 5.0 electrical characteristics s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 38 5.3.2 system bus read/write ii (68 family mpu) *1. t cyc6 indicates the cycle time during which cs e = ?? it does not mean the cycle time of signal e. *2. each of the values where v ss = ?.0v is about 200% of that where v ss = ?.0v (i.e., the listed value). *3. the rise or fall time of input signals should be less than 15 ns. ta = ?0 to 75 c, v ss = ?.0v 10%, unit: ns signal symbol parameter min. max. condition a 0 , cs r/w t cyc6 * 1 t aw6 t ah6 system cycle time address setup time address hold time 1000 20 10 d 0 ? 7 t ds6 data setup time 80 t dh6 data hold time 10 t oh6 output disable time 10 60 cl = 100pf t acc6 access time 90 et ew enable pulse width read 100 write 80 e r/w a0, cs d0 ~ d7 d0 ~ d7 (write) t cyc6 t aw6 t ew t ah6 t dh6 t ds6 t acc6 t oh6 (read)
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 39 5.0 electrical characteristics 5.3.3 ?5.3.3.2 5.3.3 display control timing 5.3.3.1 input timing 5.3.3.2 output timing *1. the listed fr input delay time applies to the SED1540 (slave). the listed fr output delay time applies to the SED1540 (master). *2. each of the values where v ss = ?.0v is about 200% of that where v ss = ?.0v (i.e., the listed value). ta = ?0 to 75 c, v ss = ?.0v 10% unit: m s (t wlcl , t whcl , t dfr ), ns (tr, tf) signal symbol parameter min. typ. max. condition cl t wlcl low level pulse width 35 t whcl high level pulse width 35 t r rise time 30 150 t f fall time 30 150 fr t dfr fr delay time ?.0 0.2 2.0 ta = ?0 to 75 c, v ss = ?.0v 10%, unit: m s signal symbol parameter min. typ. max. condition fr t dfr fr delay time 0.2 0.4 cl = 100pf cl fr t wlcl t whcl t dfr t f t r (osc1)
5.3.3.2 ?5.3.3.2 5.0 electrical characteristics s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 40 this page intentionally blank
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 41 6.0 mpu interface 6.0 ?6.1 6.0 mpu interface 6.1 80 family mpu v cc v dd a 0 a iorq 7 a 2 ~ d rd wr res gnd 7 d 0 ~ reset a a cs 0 d rd wr res 7 d 0 ~ mpu SED1540 decoder v ss v s
6.2 ?6.2 6.0 mpu interface s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 42 6.2 68 family mpu v cc v dd a 0 a vma 13 a 0 ~ d r/w e res gnd 7 d 0 ~ reset a a cs 0 d e r/w res 7 d 0 ~ mpu SED1540 decoder v ss v s
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 43 7.0 lcd driver interconnections 7.0 ?7.2 7.0 lcd driver interconnections 7.1 SED1540 - SED1540 (internal oscillation) 7.2 SED1540 - SED1540 (external clock operation) *1. for connection to more than one slave lsi, a cmos buffer must be used. *2. for use as the master slave, the same duty must be set. v ss com to lcd to lcd seg m/s rf *1 osc1 osc2 fr v dd SED1540 master to lcd seg osc1 osc2 fr SED1540 slave m/s ( ) v ss com to lcd to lcd seg m/s *1 external clock osc1 osc2 fr v dd SED1540 master to lcd seg osc1 osc2 fr SED1540 slave m/s ( )
7.2 ?7.2 7.0 lcd driver interconnections s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 44 this page intentionally blank
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 45 8.0 typical connections with lcd panel 8.0 ?8.1 8.0 typical connections with lcd panel 8.1 typical connections with lcd panel the slave ic may be omitted in this conneciton. the panel can be driven with the master ic alone. SED1540 slave seg SED1540 slave seg com segment type lcd
8.1 ?8.1 8.0 typical connections with lcd panel s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 46 this page intentionally blank
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 47 9.0 package dimensions 9.0 ?9.1 9.0 package dimensions 9.1 plastic qfp 5-100 pin 19.6 0.4 index 81 100 50 31 130 80 51 25.6 0.4 20 0.1 0.65 0.1 0.30 0.1 14 0.1 1.5 0.3 0.15 0.05 2.7 0.1 0 ~12 2.8
9.1 ?9.1 9.0 package dimensions s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 48 this page intentionally blank
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 49 10.0 pad layout 10.0 ?10.1 10.0 pad layout 10.1 pad layout 1 100 95 90 85 35 40 45 50 5 10 SED1540d 0a 15 20 25 30 80 75 70 65 60 55 y x 7.04 mm 4.80 mm
10.1.1 ?10.1.2 10.0 pad layout s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 50 10.1.1 al pad 10.1.2 au bump pad chip speci?ation dimensions die size 4.80 x 7.04 x 0.525 mm pad size 100 x 100 m m chip speci?ation dimensions minimum bump pitch 199 m m bump height 20 m m + 10/? m m bump size 132 x 111 m m 20 m m
s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 51 10.0 pad layout 10.2 ?10.2 10.2 pad coordinates unit: m m pad no. pin name x y pad no. pin name x y pad no. pin name x y 1 sed71 159 6507 35 sed37 1302 159 69 sed3 4641 4148 2 sed70 159 6308 36 sed36 1502 159 70 sed2 4641 4347 3 sed69 159 6108 37 sed35 1701 159 71 sed1 4641 4547 4 sed68 159 5909 38 sed34 1901 159 72 sed0 4641 4789 5 sed67 159 5709 39 sed33 2100 159 73 a 0 4641 5048 6 sed66 159 5510 40 sed32 2300 159 74 osc1 4641 5247 7 sed65 159 5310 41 sed31 2499 159 75 osc2 4641 5447 8 sed64 159 5111 42 sed30 2699 159 76 e(rd ) 4641 5646 9 sed63 159 4911 43 sed29 2898 159 77 r/w (wr ) 4641 5846 10 sed62 159 4712 44 sed28 3098 159 78 v ss 4641 6107 11 sed61 159 4512 45 sed27 3297 159 79 db0 4641 6307 12 sed60 159 4169 46 sed26 3497 159 80 db1 4641 6506 13 sed59 159 3969 47 sed25 3896 159 81 db2 4295 6884 14 sed58 159 3770 48 sed24 3895 159 82 db3 4095 6884 15 sed57 159 3570 49 sed23 4095 159 83 db4 3896 6884 16 sed56 159 3371 50 sed22 4295 159 84 db5 3686 6884 17 sed55 159 3075 51 sed21 4641 482 85 db6 3497 6884 18 sed54 159 2876 52 sed20 4641 681 86 db7 3297 6884 19 sed53 159 2576 53 sed19 4641 881 87 v dd 3098 6884 20 sed52 159 2477 54 sed18 4641 1080 88 res 2858 6884 21 sed51 159 2277 55 sed17 4641 1280 89 fr 2699 6884 22 sed50 159 2078 56 sed16 4641 1479 90 v 3 2499 6884 23 sed49 159 1878 57 sed15 4641 1679 91 cs 2300 6884 24 sed48 159 1679 58 sed14 4641 1878 92 mc 2100 6884 25 sed47 159 1479 59 sed13 4641 2078 93 m/s 1901 6884 26 sed46 159 1280 60 sed12 4641 2277 94 v 2 1701 6884 27 sed45 159 1080 61 sed11 4641 2477 95 v 1 1502 6884 28 sed44 159 881 62 sed10 4641 2676 96 com 0 1302 6884 29 sed43 159 681 63 sed9 4641 2875 97 com 1 1103 6884 30 sed42 159 482 64 sed8 4641 3075 98 com 2 903 6884 31 sed41 504 153 65 sed7 4641 3275 99 com 3 704 6884 32 sed40 704 153 66 sed6 4641 3474 100 sed72 504 6884 33 sed39 903 153 67 sed5 4641 3574 34 sed38 1103 153 68 sed4 4641 3948
10.2 ?10.2 10.0 pad layout s-mos systems, inc. ?150 river oaks parkway ?san jose, ca 95134 ?tel: (408) 922-0200 ?fax: (408) 922-0238 372-1.0 52 s-mos assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, in- cluding any claim for (a) copyright or patent infringement or (b) direct, indirect, special or con- sequential damages. there are no warranties extended or granted by this document. the information herein is subject to change without notice from s-mos. october 1996 ?copyright 1996 s-mos systems, inc. printed in u.s.a. 372-1.0

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